RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm

Incremental Timing Driven Placement

Standard cell layouts may need only slight modifications to meet timing constraints. In these situations, general purpose algorithms, which consider numerous parameters of the layout, may be too time consuming or too coarse to make the changes where needed. This paper presents an incremental timing driven placement algorithm designed to “cleanup” a handful of critical paths in a previously plac...

A new layout-driven timing model for incremental layout optimization

In this paper we present a new layout-driven timing model based on Asymptotic Waveform Evaluation (AWE) for improved timing analysis during routing. Our model enables the bottom-up computation of interconnect tree moments, and can be easily integrated with such a global router. Such an integration achieves incremental layout optimization, i.e., timing analysis and routing are tightly coupled, w...

Timing-Driven Interconnect Synthesis

In this chapter we address performance-driven interconnect synthesis, which seeks to optimize circuit performance by minimizing signal delays to critical sinks. Timing-driven wiring geometries are in general quite different from optimal-area (i.e., Steiner) interconnect trees, especially as die sizes continue to grow while feature dimensions steadily shrink. The exposition below focuses on sele...

Power and Timing Driven Physical Design Automation

Timing-driven partitioning and timing optimization of mixedstatic-domino implementations

| Domino logic is a circuit family that is wellsuited to implementing high-speed circuits. Synthesis of domino circuits is more complex than static logic synthesis due to the non-inverting nature of the logic and the complex timing relationships associated with the clock scheme. In this paper, we address several problems along a domino synthesis ow. We mainly consider the problem of partitionin...